How to Read This Lesson

UVM-SystemC is methodology in C++ clothing. Keep the verification intent in view: reusable components, controlled stimulus, reporting, and phase-aware execution.

Sequence Items and the UVM Factory

In UVM-SystemC, data objects that flow through the sequencer to the driver are called uvm_sequence_items. Because these items are highly dynamic (created, copied, and randomized constantly), they must be registered with the UVM Factory.

While you could manually write the do_copy, do_print, and do_compare methods, UVM-SystemC provides macros to automate this.

Source and LRM Trail

For UVM-SystemC, use Docs/LRMs/uvm-systemc-language-reference-manual.pdf as the methodology contract. In source, inspect .codex-src/uvm-systemc/src/uvmsc: components, phases, factory macros, sequences, sequencers, TLM ports, reporting, and configuration helpers.

The C++ Kernel Reality: Macro Expansion

To a C++ engineer, macros can be dangerous, but in UVM-SystemC they are strictly necessary to mimic SystemVerilog reflection.

If you expand the Accellera macro UVM_OBJECT_UTILS_BEGIN(bus_transaction), it injects a static uvm_object_registry<bus_transaction> typedef inside your class. This registry inserts your class into the global UVM factory map before sc_main even begins. It also overrides virtual methods like get_type_name(), create(), and clone().

The UVM_FIELD_INT macro goes further. It overrides the internal __m_uvm_field_automation() callback. When you call copy(), print(), or pack(), the kernel passes a uvm_packer or uvm_printer object to this callback. The macro injects code that dynamically pushes your C++ member variables into these packer objects based on the bitwise flags (like UVM_ALL_ON | UVM_HEX).

The Field Macros

Here is a complete, compilable example showing how to build a TLM-style bus transaction using UVM macros.

#include <systemc>
#include <uvm>
 
class bus_transaction : public uvm::uvm_sequence_item {
public:
    unsigned int address;
    unsigned int data;
    bool is_read;
 
    // 1. Register with the factory and open the automation block
    // Injects static uvm_object_registry and virtual overrides
    UVM_OBJECT_UTILS_BEGIN(bus_transaction);
        // 2. Automate copy, compare, and print
        // Injects code into __m_uvm_field_automation(uvm_object_wrapper&, int)
        UVM_FIELD_INT(address, uvm::UVM_ALL_ON | uvm::UVM_HEX);
        UVM_FIELD_INT(data, uvm::UVM_ALL_ON | uvm::UVM_HEX);
        UVM_FIELD_INT(is_read, uvm::UVM_ALL_ON);
    UVM_OBJECT_UTILS_END
 
    // Constructor required by UVM
    bus_transaction(const std::string& name = "bus_transaction") 
        : uvm::uvm_sequence_item(name), address(0), data(0), is_read(false) {}
};
 
class test_env : public uvm::uvm_env {
public:
    UVM_COMPONENT_UTILS(test_env);
 
    test_env(uvm::uvm_component_name name) : uvm::uvm_env(name) {}
 
    void run_phase(uvm::uvm_phase& phase) {
        phase.raise_objection(this);
 
        // Factory creation (utilizes the registry injected by UVM_OBJECT_UTILS)
        bus_transaction* tx1 = bus_transaction::type_id::create("tx1");
        tx1->address = 0x1000;
        tx1->data = 0xDEADBEEF;
 
        bus_transaction* tx2 = bus_transaction::type_id::create("tx2");
        
        // Automated deep copy (utilizes __m_uvm_field_automation)
        tx2->copy(tx1);
 
        // Automated compare
        if (tx2->compare(tx1)) {
            UVM_INFO("TEST", "Transactions match exactly!", uvm::UVM_LOW);
        }
 
        // Automated print
        tx1->print();
 
        phase.drop_objection(this);
    }
};
 
class my_test : public uvm::uvm_test {
public:
    test_env* env;
    UVM_COMPONENT_UTILS(my_test);
 
    my_test(uvm::uvm_component_name name) : uvm::uvm_test(name) {}
 
    void build_phase(uvm::uvm_phase& phase) {
        env = test_env::type_id::create("env", this);
    }
};
 
int sc_main(int argc, char* argv[]) {
    uvm::uvm_root::get()->run_test("my_test");
    return 0;
}

Output

When you execute tx1->print(), the UVM_FIELD_* macros automatically format the output into an organized table showing the hierarchy, type, size, and value of every field! This saves thousands of lines of boilerplate code in complex verification environments.

UVM-SystemC Sequence Item Macros