Introduction to SystemC

SystemC is a C++ class library and simulation kernel for modeling systems whose behavior is naturally concurrent: processors, buses, accelerators, interconnects, memories, peripherals, firmware-visible registers, and virtual platforms.

It is not a replacement syntax for Verilog or VHDL. It is C++ used with a hardware-oriented library. The library gives you modules, ports, signals, events, time, processes, and transaction-level modeling. Your compiler still sees C++, but the SystemC kernel sees a network of objects that can be elaborated, scheduled, and simulated.

Why SystemC Exists

Hardware teams often need answers before RTL exists:

• Does this architecture have enough memory bandwidth?
• Can firmware boot before the chip is built?
• Which DMA shape gives the best latency?
• How much timing detail is needed for a performance question?
• Can a testbench drive a model at transaction level before signal-level detail is ready?

SystemC fills that space by letting you model at different abstraction levels. You can write a cycle-accurate block, a loosely timed bus model, or a fast functional model in the same language.

The Core Mental Model

A SystemC executable has two lives. First, normal C++ constructs objects. Then the SystemC kernel elaborates those objects into a simulation hierarchy and runs registered processes.

#include <systemc>
using namespace sc_core;
 
SC_MODULE(Hello) {
  SC_CTOR(Hello) {
    SC_METHOD(say_hello);
  }
 
  void say_hello() {
    std::cout << "hello at " << sc_time_stamp() << "\n";
  }
};
 
int sc_main(int, char*[]) {
  Hello top{"top"};
  sc_start();
  return 0;
}

The important part is not the greeting. It is the registration. SC_METHOD(say_hello) tells the kernel that a member function is a process. sc_start() hands control to the scheduler. From that point on, time, events, and process readiness decide what runs.

SystemC Is Useful Because It Is Layered

At the low level, you can model signals, clocks, and sensitivity like RTL. At the system level, you can model a memory transaction as a function call with a delay. Between those extremes, you can decide how much timing detail is worth paying for.

That is the design tradeoff this site keeps returning to: use the simplest model that answers the engineering question, then add detail where the question demands it.

What This Course Covers

This site is organized like a long-form tutorial:

• C++ setup and the shape of a SystemC program
• Modules, hierarchy, constructors, and elaboration
• Processes, sensitivity, events, waits, and delta cycles
• Ports, interfaces, exports, channels, and binding
• Signals, resolved signals, clocks, and writer policies
• TLM-2.0 payloads, sockets, timing, and protocol phases
• Source-code reading: scheduler, signals, ports, exports, sockets, and process control
• Practical patterns for virtual platforms and deployable documentation

The source-code chapters point to the official Accellera reference implementation at github.com/accellera-official/systemc. The goal is not to memorize every private member. The goal is to recognize the architecture behind the public API.