LRM Bridge: Datatypes | Learn SystemC

SystemC provides specialized hardware datatypes because standard C++ types (int, bool) cannot natively model arbitrary bus widths, 4-state logic (X/Z states), or bit-level slicing.

End-to-End Datatypes Example

This fully compliant sc_main demonstrates the usage of 4-state logic (sc_logic), arbitrary width bit vectors (sc_bv), signed integer vectors (sc_int), and fixed-point math (sc_fixed).

#define SC_INCLUDE_FX // Required to enable fixed-point datatypes
#include <systemc>
 
SC_MODULE(DatatypesDemo) {
    SC_CTOR(DatatypesDemo) {
        SC_METHOD(demo_logic_and_vectors);
        SC_METHOD(demo_fixed_point);
    }
 
    void demo_logic_and_vectors() {
        // 1. 4-State Logic (0, 1, Z, X)
        sc_dt::sc_logic signal_state = sc_dt::Log_Z; // High-impedance
        
        // 2. Bit Vectors (2-state, arbitrary width)
        sc_dt::sc_bv<12> control_bus = "101011001111";
        
        // 3. Logic Vectors (4-state, arbitrary width)
        sc_dt::sc_lv<8> data_bus = "10ZX0011";
 
        // 4. Fixed-width signed integers
        sc_dt::sc_int<9> signed_val = -25;
        
        // Bit-slicing proxy demonstration:
        // Extract the upper 4 bits of control_bus and assign to a new 4-bit vector
        sc_dt::sc_bv<4> upper_nibble = control_bus.range(11, 8);
        
        std::cout << "--- Logic & Vectors ---" << std::endl;
        std::cout << "Signal: " << signal_state << std::endl;
        std::cout << "Control Bus: " << control_bus << std::endl;
        std::cout << "Upper Nibble: " << upper_nibble << std::endl;
        std::cout << "Signed Val (9-bit): " << signed_val << std::endl;
    }
 
    void demo_fixed_point() {
        std::cout << "--- Fixed Point Math ---" << std::endl;
        
        // 16 total bits, 4 bits for the integer part (12 bits fractional)
        sc_dt::sc_fixed<16, 4> a = 3.14159;
        sc_dt::sc_fixed<16, 4> b = -1.5;
        
        // The result of the multiplication is truncated/rounded automatically
        // according to the sc_fixed quantization modes defined in the LRM.
        sc_dt::sc_fixed<16, 4> result = a * b;
        
        std::cout << "3.14159 * -1.5 in Q4.12 fixed-point = " << result.to_double() << std::endl;
    }
};
 
int sc_main(int argc, char* argv[]) {
    DatatypesDemo demo("demo");
    sc_core::sc_start();
    return 0;
}

Type Breakdown

Logic and Bit Vectors

sc_logic: Represents four-state logic ('0', '1', 'Z' (high-impedance), 'X' (unknown)). Use only when modeling tri-state buses or uninitialized hardware memory.
sc_bv<W>: A two-state bit vector of arbitrary width W.
sc_lv<W>: A four-state logic vector.

Fixed Width Integers

sc_int<W> and sc_uint<W> (1 to 64 bits): Fast signed/unsigned fixed-width arithmetic.
sc_bigint<W> and sc_biguint<W>: Arbitrary precision arithmetic. Use these sparingly, as mathematical operations on >64-bit numbers in software are computationally heavy.

Fixed-Point (`sc_fixed`)

To use fixed-point types, you must define #define SC_INCLUDE_FX before including <systemc>. sc_fixed<WL, IWL> models word length (WL) and integer word length (IWL). The LRM provides exhaustive quantization and overflow modes (e.g., SC_RND, SC_TRN, SC_SAT) for DSP and AMS modeling.

Practical Modeling Discipline

While bit selection proxies (bus.range(7, 0) = byte;) are syntactically convenient, dense bit-slicing equations are notoriously difficult to debug. For Virtual Platforms and TLM, prefer standard C++ types (uint32_t, uint64_t) for data payloads and registers to maximize simulation speed, resorting to sc_bv only when bit-accurate pin modeling is explicitly required.