LRM Roadmap: How the Standards Fit Together

This site uses the LRMs in Docs/LRMs as reference sources, but the public lessons are written as explanations. The goal is to help you read the standards without feeling like you were dropped into an index.

The repository includes these reference manuals:

• IEEE 1666-2023 SystemC Language Reference Manual: The core simulation kernel, events, and TLM standard.
• SystemC AMS 2.0 Language Reference Manual: Analog and Mixed-Signal extensions.
• SystemC CCI 1.0 Language Reference Manual: Configuration, Control, and Inspection API.
• UVM-SystemC Language Reference Manual: Universal Verification Methodology for SystemC.

How to Think About the Stack

SystemC 1666 is the base language and simulation kernel. It defines modules, processes, events, time, ports, exports, channels, datatypes, reports, tracing, and the Transaction Level Modeling (TLM) 2.0 standard. All other LRMs build on this discrete-event foundation.

SystemC AMS adds analog/mixed-signal modeling styles on top of SystemC. Its central ideas are timed data flow (TDF), conservative electrical networks, and linear signal flow (LSF), solving analog equations in conjunction with the discrete-event solver.

SystemC CCI adds configuration, control, and inspection. It provides standard APIs to expose parameters (cci_param), broker access, and track where configuration values originated, heavily utilized in Virtual Platforms.

UVM-SystemC adds verification methodology: components, factory, phases, sequences, sequencers, configuration, reporting, TLM ports, and register abstractions, porting SystemVerilog UVM to C++.

What "Between Learning Site and LRM" Means

An LRM strictly dictates legal syntax, elaboration phases, memory management, and standard compliance. It tells you what is defined. A learning site tells you how to think. These lessons aim to do both:

• Name the LRM area explicitly.
• Explain why it exists in the hardware modeling ecosystem.
• Provide exhaustive, 100% compilable, end-to-end sc_main modeling patterns.
• Warn about common C++ and SystemC mistakes.

If a lesson references standard definitions, treat it as exhaustive technical guidance compliant with the IEEE specs. Every code snippet provided in these LRM chapters is a fully independent model you can compile and run directly to observe the LRM's behavior firsthand.

Reading Order

If you are new, start with chapters 1 through 6. Then read the LRM bridge chapters:

1. SystemC 1666 Semantics and Core Classes: Elaboration, execution phases, and process macros.
2. Ports, Exports, Channels, Datatypes, and TLM: The structural and transaction-level backbone.
3. AMS Models of Computation: Timed Data Flow and solver synchronization.
4. CCI Parameters and Brokers: Tool-independent IP configuration.
5. UVM-SystemC Verification Architecture: Testbenches and constrained randomization.

That order ensures the LRMs become a structured technical guide rather than an overwhelming reference index.