Introduction to High-Level Synthesis (HLS)

The SystemC Synthesizable Subset (often referenced via the Accellera SystemC Synthesis Working Group) defines the subset of the SystemC C++ class library that can be reliably synthesized into register-transfer level (RTL) hardware by High-Level Synthesis (HLS) tools.

While SystemC is an incredibly powerful language for simulation and virtual prototyping, not everything you can write in C++ can be physically built in silicon. For example, dynamically allocating memory on the heap using new or malloc during the middle of a hardware simulation has no physical equivalent in a fixed silicon area.

The Goal of the Synthesizable Subset

The goal of the synthesis subset is to provide a standardized, common denominator of SystemC constructs that EDA vendors (like Cadence, Synopsys, Siemens, etc.) agree upon. If you write your SystemC code using only these constructs, you are guaranteed that an HLS tool can compile your C++ code into Verilog or VHDL.

Key Restrictions

To make C++ synthesizable, several major restrictions are enforced:

1. No Dynamic Allocation After Elaboration: You cannot dynamically allocate memory or objects after the start_of_simulation() phase. All hardware must be statically known.
2. No Dynamic Processes: Functions like sc_spawn are generally not synthesizable. You must use static SC_METHOD or SC_CTHREAD registrations.
3. Restricted Pointers: Pointer arithmetic is heavily restricted or outright banned. Pointers can only be used if the HLS tool can statically determine exactly what they point to at compile time.
4. No Recursion: Hardware cannot easily implement arbitrary recursion without an infinite unbounded stack. Recursive function calls are not synthesizable.
5. Standard Library Limits: Standard C++ library features like std::vector, std::map, or file I/O (std::cout, fstream) are meant for simulation only and cannot be synthesized into silicon.

In the next tutorial, we will explore which specific SystemC datatypes are supported for synthesis.