C++ Prerequisites for SystemC

How to Read This Lesson

Read this as the C++ toolkit you will keep reusing throughout the course. SystemC feels much less mysterious once you can see the ordinary C++ mechanisms underneath its hardware-modeling vocabulary.

Before diving into SystemC, it is crucial to understand that SystemC is not a new language. It is entirely built as a C++ class library. If you are coming from Verilog or VHDL, you might be tempted to treat SystemC like a hardware description language. However, if you do not understand the underlying C++, you will quickly become frustrated when the compiler throws massive template errors.

This page outlines exactly what C++ concepts you must master before proceeding.

[!NOTE]
Disclaimer: The SystemC code shown in this chapter is strictly to demonstrate how C++ concepts are leveraged. We will dive deep into how these SystemC components actually work in their respective chapters.

Standard and source context

For this foundation lesson, keep three references close: Docs/LRMs/SystemC_LRM_1666-2023.pdf for portable semantics, Accellera SystemC GitHub repository for kernel behavior, and Accellera SystemC GitHub repository for bit-accurate C++ types. When this lesson mentions a macro or type, the useful habit is to ask which C++ class the macro eventually creates.

1. Object-Oriented Programming (OOP)

SystemC modules (sc_module) are just C++ classes. You need to be deeply comfortable with:

• Classes and Structs: Creating them, member variables, and member functions.
• Constructors: SystemC relies heavily on constructors (SC_CTOR) to register processes and bind ports.
• Inheritance: sc_module inherits from sc_object. You will frequently use public inheritance when defining custom interfaces.
• Polymorphism and Virtual Functions: In TLM (Transaction Level Modeling), you will define purely virtual interfaces and implement them in your target modules.

2. Pointers and References

Hardware ports are essentially safe pointers to signals.

• Pass-by-Reference (&): Passing large transaction payloads efficiently.
• Pointers (*): Dynamically allocating modules, or passing pointers to arrays.
• Smart Pointers: In advanced TLM and SCV (SystemC Verification Library), you will use scv_smart_ptr to handle memory automatically and avoid segmentation faults.

3. C++ Templates

SystemC ports, signals, and FIFOs are templated classes. When you write sc_in<bool>, you are instantiating an sc_in template for the boolean type.

You must understand:

• How to pass basic types to templates (sc_signal<int>).
• How to pass user-defined structs to templates (sc_signal<MyStruct>).
• Operator Overloading: SystemC overloads the << operator for sensitivity lists and port binding, and the = operator for reading/writing signals. It is not bit-shifting; it is C++ operator overloading.

4. The Standard Template Library (STL)

You will not write your own linked lists. You will use the STL.

• std::vector for dynamic arrays of ports or modules.
• std::string for dynamic module naming.
• std::cout and std::endl for simulation logging.

Summary

If any of these concepts are entirely foreign to you, please pause and read through a comprehensive C++ programming guide. SystemC is incredibly powerful, but its power comes from leveraging advanced C++ paradigms to mimic hardware concurrency.

[!IMPORTANT] This guide provides a conceptual overview. For production-level system design, always refer to the IEEE 1666-2023 standard and the Accellera proof-of-concept implementation headers to understand the underlying C++ template expansion.

Once you are comfortable with C++, proceed to the next tutorial to install the Accellera SystemC library.

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