# LearnSystemC Quick Reference

Use this as a memory aid beside the free lessons at https://www.learn-systemc.com.

This Markdown file is also suitable as a compact context attachment for an AI
assistant. For the full course corpus, use:
https://www.learn-systemc.com/systemc-ai-context.md

## 1. Minimal module

```cpp
#include <systemc>
using namespace sc_core;

SC_MODULE(Counter) {
  sc_in<bool> clk;
  sc_out<unsigned> value;

  void tick() {
    value.write(value.read() + 1);
  }

  SC_CTOR(Counter) {
    SC_METHOD(tick);
    sensitive << clk.pos();
  }
};
```

## 2. Process choices

```text
SC_METHOD(fn)
  Runs to completion when triggered. It must not call wait().

SC_THREAD(fn)
  May call wait() and resume later. It models sequential behavior over time.

SC_CTHREAD(fn, clk.pos())
  Clocked thread style commonly used for synthesis-oriented models.
```

## 3. Time and events

```cpp
wait(10, SC_NS);
wait(event);
event.notify();              // immediate notification
event.notify(SC_ZERO_TIME);  // next delta cycle
event.notify(5, SC_NS);      // timed notification
```

Remember: sc_signal writes are deferred. A write becomes visible during the
kernel update phase, not necessarily on the next C++ statement.

## 4. Ports, interfaces, and channels

```text
sc_in<T>   input;
sc_out<T>  output;
sc_signal<T> signal;

Port       = what a module requires
Interface  = callable contract
Channel    = object implementing an interface
Export     = interface exposed through hierarchy
```

## 5. FIFO communication

```cpp
sc_fifo<int> fifo{"fifo", 16};
fifo.write(42);
int value = fifo.read();
```

Blocking reads and writes belong in thread processes because they may wait.

## 6. TLM-2.0 blocking transport

```cpp
tlm::tlm_generic_payload trans;
sc_time delay = SC_ZERO_TIME;

trans.set_command(tlm::TLM_READ_COMMAND);
trans.set_address(address);
trans.set_data_ptr(data);
trans.set_data_length(length);
trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);

initiator_socket->b_transport(trans, delay);
```

Check trans.is_response_error() after transport. Inspect get_response_status()
when you need the specific target response.

## 7. Debugging checklist

- Did elaboration finish before simulation started?
- Is every required port bound exactly as intended?
- Are you expecting a deferred sc_signal write to read back immediately?
- Can the current process legally call wait()?
- Is a TLM address global, local, or translated by a router?
- Is a behavior required by the LRM or specific to one implementation?

## 8. Read next

Setup:
https://www.learn-systemc.com/tutorials/002-installation-and-setup

Ports and channels:
https://www.learn-systemc.com/tutorials/010-ports-interfaces-exports-and-channels

Processes and time:
https://www.learn-systemc.com/tutorials/007-processes-events-and-time

TLM-2.0:
https://www.learn-systemc.com/tutorials/014-tlm-2-0-generic-payloads-and-sockets

Source-reading workflow:
https://www.learn-systemc.com/tutorials/024-a-practical-systemc-source-reading-workflow

This quick reference is intentionally compact. Use the linked lessons for LRM
context, Accellera source trails, examples, and the engineering tradeoffs.