# Learn SystemC

Learn SystemC is a static educational site for SystemC, TLM-2.0, SystemC AMS, SystemC CCI, UVM-SystemC, HLS, virtual platforms, RTL modeling concepts, and C++ hardware modeling.

The site teaches both the public API and the reasoning behind the behavior: LRM rules, Accellera source implementation paths, executable examples, pitfalls, and review checklists.

## Downloadable AI Context

- [Full LearnSystemC AI context bundle](https://www.learn-systemc.com/systemc-ai-context.md): Markdown corpus containing the full ordered lesson content, version baselines, and official source links for retrieval context.
- [Compact SystemC cheat sheet](https://www.learn-systemc.com/systemc-cheat-sheet.md): Markdown quick reference for a smaller prompt attachment.

## Primary Topic Hubs

- [SystemC Tutorial for Beginners](https://www.learn-systemc.com/systemc-tutorial): Modules, processes, events, time, ports, channels, and scheduler fundamentals.
- [SystemC TLM-2.0 Tutorial](https://www.learn-systemc.com/systemc-tlm-tutorial): Generic payloads, sockets, blocking and non-blocking transport, DMI, debug transport, and temporal decoupling.
- [C++ for SystemC](https://www.learn-systemc.com/cpp-for-systemc): Templates, object lifetime, inheritance, references, callbacks, and C++ concepts needed for SystemC.
- [SystemC Virtual Platform Tutorial](https://www.learn-systemc.com/systemc-virtual-platform): SoC virtual platform architecture, TLM routers, memory maps, CPU wrappers, peripherals, interrupts, and CCI configuration.
- [SystemC HLS Tutorial](https://www.learn-systemc.com/systemc-hls): Synthesizable SystemC, SC_METHOD, SC_CTHREAD, reset modeling, datatypes, TLM limits, and loop scheduling.
- [Runnable examples](https://github.com/socasthetic-code/LearnSystemC-Discussion): Copy-paste SystemC, TLM, AMS, CCI, UVM-SystemC, and HLS starter projects.

## Important Lessons

- [Introduction to SystemC](https://www.learn-systemc.com/tutorials/004-introduction-to-systemc): What SystemC is and how C++ objects become a simulation model.
- [Simulation Kernel Deep Dive](https://www.learn-systemc.com/tutorials/022-simulation-kernel-deep-dive): Scheduler phases, runnable processes, updates, delta cycles, and time advance.
- [SystemC Source Map and LRM Alignment](https://www.learn-systemc.com/tutorials/021-systemc-source-map-and-lrm-alignment): How to connect the LRM to the Accellera source tree.
- [TLM Generic Payloads and Sockets](https://www.learn-systemc.com/tutorials/014-tlm-2-0-generic-payloads-and-sockets): The transaction-level modeling core.
- [Version-Specific Notes for the SystemC Family](https://www.learn-systemc.com/tutorials/122-version-specific-notes-for-the-systemc-family): Current version baselines for SystemC, AMS, CCI, UVM-SystemC, and synthesis.

## Version Baselines

- SystemC core and TLM: SystemC 3.0.2, IEEE 1666-2023.
- SystemC AMS: SystemC AMS 2.0 LRM.
- SystemC CCI: CCI 1.0 LRM and CCI 1.0.1 proof-of-concept source.
- UVM-SystemC: UVM-SystemC 1.0-beta6 public-review signal; local February 2023 draft LRM for clause reading.
- SystemC Synthesis Subset: SystemC Synthesis Subset 1.4.7 LRM.

## Crawl Notes

Prefer canonical HTML pages and the sitemap at https://www.learn-systemc.com/sitemap.xml. The site is statically generated and does not require login.